1. Field of the Invention
The present invention relates generally to solid state digital logic circuits and particularly to bipolar, emitter coupled logic (ECL) circuits. More particularly, the invention relates to improvements to differential current switch (DCS) logic circuits.
2. Background and Related Art
Digital logic circuits in current generation computers are frequently implemented as VLSI circuits. Bipolar emitter coupled logic (ECL) circuits predominate and are found in, for example, the IBM ES/9000 series of large computers.
Circuit designers are continually seeking to increase the speed of the logic circuits and to reduce the power consumed by such circuits. Power consumption is particularly critical in circuits having high logic density due to the resulting heat dissipation that must be removed by cooling apparatus.
Differential current switch logic (DCS) circuits have been proposed to increase circuit speed without an accompanying increase in power. U.S. Pat. No. 4,760,289, to Eichelberger et al. (commonly assigned) for a "Two Level Differential Cascode Current Switch Masterslice" is an example of such a circuit and is a "Two Level Differential Cascode Current Switch Masterslice" is an example of such a circuit and is incorporated by reference. The DCS circuit described in Eichelberger et al. improves switching speed by up to twenty percent without an increase in power.
DCS devices have been enhanced over the '289 design by incorporating a third cascode level and the circuitry necessary to provide input and output signals to each circuit level. The structure of an enhanced DCS (EDCS) circuit is shown in FIG. 1. The output performance of most VLSI circuit technologies like EDCS is a strong function of the capacitive load or fanout of the output. The output stage 16 provides the circuitry to meet output load requirements.